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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad5231 * one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-470 0 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 nonvolatile memory, 1024-position digital potentiometers functional block diagram rdac register eemem1 digital register eemem control 28 bytes user eemem eemem2 ad5231 rdac digital output buffer cs clk wp pr sdi gnd sdo rdy sdo serial interface addr decode v dd v ss a w b o1 o2 sdi 2 code ?decimal 100 75 0 0 1023256 r wa (d), r wb (d) ?percent of nominal ?% r ab 512 768 50 25 r wb r wa figure 1. r wa (d) and r wb (d) vs. decimal code features nonvolatile memory 1 preset maintains wiper settings 1024-position resolution full monotonic operation 10 k , 50 k , and 100 k terminal resistance permanent memory write-protection wiper settings read back linear increment/decrement log taper increment/decrement push button increment/decrement compatible spi compatible serial interface with readback function 3 v to 5 v single supply or 2.5 v dual supply 28 bytes user nonvolatile memory for constant storage 100 year typical data retention t a = 55 c applications mechanical potentiometer replacement instrumentation: gain, offset adjustment programmable voltage to current conversion programmable filters, delays, time constants line impedance matching power supply adjustment low resolution dac replacement general description the ad5231 provides nonvolatile memory digitally controlled potentiometers 2 with 1024-position resolution. these devices perform the same electronic adjustment function as a mechanical potentiometer. the ad5231s versatile programming via a stan- dard 3-wire serial interface allows 16 modes of operation and adjustment, including scratch pad programming, memory stor- ing and retrieving, increment/decrement, log taper adjustment, wiper setting read back, and extra user-defined eemem. in the scratch pad programming mode, a specific setting can be programmed directly to the rdac 2 register, which sets the resis- tance at terminals w-a and w-b. the rdac register can also be loaded with a value previously stored in the eemem 1 regis- ter. the value in the eemem can be changed or protected. when changes are made to the rdac register, the value of the new setting can be saved into the eemem. thereafter, such value will be transferred automatically to the rdac register during system power on. it is enabled by the internal preset strobe. eemem can also be retrieved through direct programming and external preset pin control. other operations include linear step increment and decrement commands such that the setting in the rdac register can be moved up or down, one step at a time. for logarithmic changes in wiper setting, a left/right bit shift command adjusts the level in 6 db steps. the ad5231 is available in thin tssop-16 package. all parts are guaranteed to operate over the extended industrial tempera- ture range of C40 c to +85 c. notes 1 the terms nonvolatile memory and eemem are used interchangeably. 2 the terms digital potentiometer and rdac are used interchangeably. * patent pending
rev. 0 C2C ad5231?pecifications electrical characteristics 10 k , 50 k , 100 k versions parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode resistor differential nonlinearity 2 r-dnl r wb, v a = nc, monotonic C1 1/2 +1.8 lsb resistor integral nonlinearity 2 r-inl r wb, v a = nc C0.2 +0.2 % fs nominal resistor tolerance r wb d = 3ff h C40 +20 % resistance temperature coefficient r ab / t 600 ppm/ c wiper resistance r w i w = 100 a, v dd = 5.5 v, 15 100 ? code = half-scale i w = 100 a, v dd = 3 v, 50 ? code = half-scale dc characteristics potentiometer divider mode resolution n 10 bits differential nonlinearity 3 dnl monotonic, t a = 25 cC1 1/2 +1 lsb monotonic, t a = C40 c or +85 c C1 +1.25 lsb integral nonlinearity 3 inl C0.4 +0.4 % fs voltage divider temperature coefficient v w / t code = half-scale 15 ppm/ c full-scale error v wfse code = full-scale C3 0 % fs zero-scale error v wzse code = zero-scale 0 +1.5 % fs resistor terminals terminal voltage range 4 v a, b, w v ss v dd v capacitance 5 a, b c a, b f = 1 mhz, measured to gnd, 50 pf code = half-scale capacitance 5 wc w f = 1 mhz, measured to gnd, 50 pf code = half-scale common-mode leakage current 5, 6 i cm v w = v dd /2 0.01 1 a digital inputs and outputs input logic high v ih with respect to gnd, v dd = 5 v 2.4 v input logic low v il with respect to gnd, v dd = 5 v 0.8 v input logic high v ih with respect to gnd, v dd = 3 v 2.1 v input logic low v il with respect to gnd, v dd = 3 v 0.6 v input logic high v ih with respect to gnd, v dd = +2.5 v, v ss = C2.5 v 2.0 v input logic low v il with respect to gnd, v dd = +2.5 v, v ss = C2.5 v 0.5 v output logic high (sdo, rdy) v oh r pull-up = 2.2 k ? to 5 v 4.9 v output logic low v ol i ol = 1.6 ma, v logic = 5 v 0.4 v input current i il v in = 0 v or v dd 2.5 a input capacitance 5 c il 4pf output current 5 i o1, i o2 v dd = 5 v, v ss = 0 v, t a = 25 c50 ma v dd = 2.5 v, v ss = 0 v, t a = 25 c7 ma power supplies single-supply power range v dd v ss = 0 v 2.7 5.5 v dual-supply power range v dd /v ss 2.25 2.75 v positive supply current i dd v ih = v dd or v il = gnd 2.7 10 a programming mode current i dd(pg) v ih = v dd or v il = gnd 40 ma read mode current 7 i dd(xfr) v ih = v dd or v il = gnd 0.3 3 9 ma negative supply current i ss v ih = v dd or v il = gnd, v dd = +2.5 v, v ss = C2.5 v 0.5 10 a power dissipation 8 p diss v ih = v dd or v il = gnd 0.018 0.05 mw power supply sensitivity 5 i o i ol p ss v dd = 5 v 10% 0.002 0.01 %/% dynamic characteristics 5, 9 bandwidth bw C3 db, r = 10 k ? /50 k ? /100 k ? 370/85/44 khz total harmonic distortion thd w v a = 1 v rms , v b = 0 v, f = 1 khz, r ab = 10 k ? 0.022 % total harmonic distortion thd w v a = 1 v rms , v b = 0 v, f = 1 khz, r ab = 50 k ? , 100 k ? 0.045 % (v dd = 3 v 10% or 5 v 10% and v ss = 0 v, v a = +v dd , v b = 0 v, ?0 c < t a < +85 c, unless otherwise noted.)
rev. 0 C3C ad5231 parameter symbol conditions min typ 1 max unit v w settling time t s v a = v dd , v b = 0 v, 1.2/3.7/7 s v w = 0.50% error band, code 000 h to 200 h for r ab = 10 k ? /50 k ? /100 k ? resistor noise voltage e n_wb r wb = 5 k ? , f = 1 khz 9 nv/ hz notes 1 typicals represent average readings at 25 c and v dd = 5 v. 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. i w ~ 50 a @ v dd = +2.7 v and i w ~ 400 a @ v dd = +5 v for the r ab = 10 k ? version, i w ~ 50 a for the r ab = 50 k ? and i w ~ 25 a for the r ab = 100 k ? version. see test circuit figure 12. 3 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output d/a converter. v a = v dd and v b = v ss . dnl specification limits of C1 lsb minimum are guaranteed monotonic operating conditions. see test circuit figure 13. 4 resistor terminals a, b, and w have no limitations on polarity with respect to each other. dual supply operat ion enables ground-referenced bipolar signal adjustment. 5 guaranteed by design and not subject to production test. 6 common-mode leakage current is a measure of the dc leakage from any terminal b and w to a common-mode bias level of v dd /2. 7 transfer (xfr) mode current is not continuous. current consumed while eemem locations are read and transferred to the rdac regi ster. see tpc 19. 8 p diss is calculated from (i dd v dd ) + (i ss v ss ). 9 all dynamic characteristics use v dd = +2.5 v and v ss = C2.5 v. specifications subject to change without notice. electrical characteristics 10 k , 50 k , 100 k versions parameter symbol conditions min typ 1 max unit interface timing characteristics 2, 3 clock cycle time (t cyc )t 1 20 ns cs setup time t 2 10 ns clk shutdown time to cs rise t 3 1t cyc input clock pulsewidth t 4 , t 5 clock level high or low 10 ns data setup time t 6 from positive clk transition 5 ns data hold time t 7 from positive clk transition 5 ns cs to sdo-spi line acquire t 8 40 ns cs to sdo-spi line release t 9 50 ns clk to sdo propagation delay 4 t 10 r p = 2.2 k ? , c l < 20 pf 50 ns clk to sdo data hold time t 11 r p = 2.2 k ? , c l < 20 pf 0 ns cs high pulsewidth 5 t 12 10 ns cs high to cs high 5 t 13 4t cyc rdy rise to cs fall t 14 0ns cs rise to rdy fall time t 15 0.1 0.15 ms read/store to nonvolatile eemem 6 t 16 applies to command 2 h , 3 h , 9 h 25 ms cs rise to clock rise/fall setup t 17 10 ms preset pulsewidth (asynchronous) t prw not shown in timing diagram 50 ms preset response time to rdy high t presp pr pulsed low to refreshed wiper positions 70 s flash/ee memory reliability endurance 7 100 k cycles data retention 8 100 years notes 1 typicals represent average readings at 25 c and v dd = 5 v. 2 guaranteed by design and not subject to production test. 3 see timing diagram for location of measured values. all input control voltages are specified with t r = t f = 2.5 ns (10% to 90% of 3 v) and timed from a voltage level of 1.5 v. switching characteristics are measured using both v dd = 3 v and 5 v. 4 propagation delay depends on value of v dd , r pull_up , and c l . see applications text. 5 valid for commands that do not activate the rdy pin. 6 rdy pin low only for commands 2, 3, 8, 9, 10, and the pr hardware pulse: cmd_8 ~ 1 s; cmd_9,10 ~0.12 s; cmd_2,3 ~20 s. device operation at t a = C40 c and v dd < +3 v extends the save time to 35 s. 7 endurance is qualified to 100,000 cycles as per jedec std. 22 method a117 and measured at C40 c, +25 c, and +85 c; typical endurance at 25 c is 700,000 cycles. 8 retention lifetime equivalent at junction temperature (t j ) = 55 c as per jedec std. 22, method a117. retention lifetime based on an activation energy of 0.6 ev will derate with junction temperature as shown in figure 20 in the flash/ee memory description section of this data sheet. the ad5231 contains 9,646 transistors. die size: 69 mil 115 mil, 7,993 sq. mil. specifications subject to change without notice. (v dd = 3 v to 5.5 v and ?0 c < t a < +85 c, unless otherwise noted.)
rev. 0 ad5231 C4C cpol = 1 t 12 t 13 t 3 t 17 t 9 t 11 t 5 t 4 t 2 t 1 clk t 8 * msb lsb out msb lsb rdy cpha = 1 t 10 t 7 t 6 t 14 t 15 t 16 *n ot defined, but normally lsb of character previously transmitted. the cpol = 1 microcontroller command aligns the incoming data to the positive edge of the clock. cs sdo sdi figure 2a. cpha = 1 timing diagram t 12 t 13 t 3 t 17 t 9 t 11 t 5 t 4 t 2 t 1 clk cpol = 0 t 8 msb out lsb sdo msb in lsb sdi rdy cpha = 0 t 10 t 7 t 6 t 14 t 15 t 16 * not defined, but normally msb of character just received. the cpol = 0 microcontroller command aligns the incoming data to the positive edge of the clock. * cs figure 2b. cpha = 0 timing diagram
rev. 0 ad5231 C5C absolute maximum ratin gs 1 (t a = 25 c, unless otherwise noted) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, +7 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v, C7 v v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v v a , v b , v w to gnd . . . . . . . . . . . . . v ss C 0.3 v, v dd + 0.3 v aCb, aCw, bCw intermittent 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ma continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ma digital inputs and output voltage to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, v dd + 0.3 v operating temperature range 3 . . . . . . . . . . . C40 c to +85 c maximum junction temperature (t j max) . . . . . . . . . 150 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c thermal resistance junction-to-ambient ja , tssop-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c/w thermal resistance junction-to-case jc , tssop-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 c/w package power dissipation = (t j max C t a )/ ja notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 3 includes programming of nonvolatile memory warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad5231 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide r ab temperature package package ordering model (k ) range ( c) description option quantity top mark * ad5231bru10 10 C40 to +85 tssop-16 ru-16 96 5231b10 ad5231bru10-reel7 10 C40 to +85 tssop-16 ru-16 1,000 5231b10 ad5231bru50 50 C40 to +85 tssop-16 ru-16 96 5231b50 AD5231BRU50-REEL7 50 C40 to +85 tssop-16 ru-16 1,000 5231b50 ad5231bru100 100 C40 to +85 tssop-16 ru-16 96 5231bc ad5231bru100-reel7 100 C40 to +85 tssop-16 ru-16 1,000 5231bc * line 1 contains adi logo symbol and the date code yyww; line 2 contains detail model number listed in this column.
rev. 0 ad5231 C6C pin configuration top view (not to scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 clk sdi sdo v ss gnd t rdy cs pr wp v dd a w ad5231 o1 b o2 pin function descriptions pin no. mnemonic description 1 o1 nonvolatile digital output #1. addr(o1) = 1 h , data bit position d0 2 clk serial input register clock pin. shifts in one bit at a time on positive clock edges. 3 sdi serial data input pin. shifts in one bit at a time on positive clock clk edges. msb loaded first. 4 sdo serial data output pin. open drain output requires external pull-up resistor. commands 9 and 10 activate the sdo output. (see instruction operation truth table, table iii.) other commands shift out the previously loaded sdi bit pattern delayed by 24 clock pulses. this allows daisy-chain operation of multiple packages. 5 gnd ground pin, logic ground reference 6v ss negative supply. connect to zero volts for single supply applications. 7t used as digital input during factory test mode. connect to v dd or v ss . 8 b b terminal of rdac 9w wiper terminal of rdac. addr(rdac1) = 0 h . 10 a a terminal of rdac1 11 v dd positive power supply pin 12 wp write protect pin. when active low, wp prevents any changes to the present contents except pr and cmd 1 and 8 will refresh the rdac register from eemem. execute on nop instruction before returning to wp high. 13 pr hardware override preset pin. refreshes the scratch pad register with current contents of the eemem register. factory default loads midscale 512 10 until eemem loaded with a new value by the user ( pr is activated at the logic high transition). 14 cs serial register chip select active low. serial register operation takes place when cs returns to logic high. 15 rdy ready. active-high open drain output. identifies completion of commands 2, 3, 8, 9, 10, and pr . 16 o2 nonvolatile digital output #2. addr(o2) = 1 h , data bit position d1.
rev. 0 ad5231 C7C code decimal 0 inl error lsb 1.5 0 1.0 1.0 0.5 256 512 768 t a = +25 c t a = +85 c t a = 40 c 1024 0.5 128 384 640 896 tpc 1. inl vs. code, t a = C40 c, +25 c, +85 c overlay, r ab = 10 k ? code decimal dnl error lsb 0 2.0 2.0 1.0 t a = +25 c t a = +85 c t a = 40 c 1.0 0 256 512 768 1024 128 384 640 896 0.5 1.5 0.5 1.5 v dd = 5v, v ss = 0v tpc 2. dnl vs. code, t a = C40 c, +25 c, +85 c overlay, r ab = 10 k ? code decimal r-inl lsb 0 1.0 1.0 0.5 t a = +85 c 0.5 0 256 512 768 1024 128 384 640 896 t a = 40 c v dd = 5v, v ss = 0v t a = +25 c tpc 3. r-inl vs. code, t a = C40 c, +25 c, +85 c overlay, r ab = 10 k ? code decimal 0 128 256 384 512 640 768 896 1024 2.0 1.5 1.0 0.5 0 2.0 1.5 1.0 0.5 r-dnl lsb v dd = 5v, v ss = 0v t a = 40 c t a = +85 c t a = +25 c tpc 4. r-dnl vs. code, t a = C40 c, +25 c, +85 c overlay, r ab = 10 k ? code decimal rheostat mode tempco ppm/ c 3000 0 256 512 768 1024 128 384 640 896 v dd = 5.5v, v ss = 0v 2500 2000 1500 1000 500 0 t a = 40 c to +85 c tpc 5. r wb / t vs. code, r ab = 10 k ? code decimal potentiometer mode tempco ppm/ c 100 0 256 512 768 1024 128 384 640 896 80 60 40 20 0 20 v dd = 5.5v, v ss = 0v t a = 40 c to +85 c v b = 0v v a = 2.00v tpc 6. r wb / t vs. code, r ab = 10 k ? typical performance characteristics
rev. 0 ad5231 C8C code decimal r w 60 0 256 512 768 1024 128 384 640 896 50 40 30 20 10 0 v dd = 2.7v, v ss = 0v t a = 25 c tpc 7. wiper-on resistance vs. code temperature c current a 4 40 0 40 80 20 20 60 100 3 2 1 0 1 i dd @ v dd /v ss = 5v/0v i ss @ v dd /v ss = 5v/0v i ss @ v dd /v ss = 2.7v/0v i dd @ v dd /v ss = 2.7v/0v tpc 8. i dd vs. temperature, r ab = 10 k ? clock frequency mhz i dd ma 0.25 048 2 6 10 12 0.20 0.15 0.10 0.05 0.00 v dd = 5v v ss = 0v midscale zero-scale full-scale tpc 9. i dd vs. clock frequency, r ab = 10 k ? frequency hz 2 0 16 1k 10k gain db 2 4 12 6 8 10 14 100k 1m f 3db = 370khz, r ab = 10k v a = 1mv rms v dd / v ss = 2.5v d = midscale f 3db = 44khz, r = 100k f 3db = 85khz, r ab = 50k tpc 10. C3 bandwidth vs. resistance. test circuit in figure 16. frequency khz 0.12 0.01 thd + noise % 0.10 0.08 0.04 0.00 0.1 1 10 r ab = 10k 100k v dd /v ss = 2.5v v a = 1v rms 100 50k 0.06 0.02 tpc 11. total harmonic distortion vs. frequency frequency hz 0 50 1k gain db 25 100k 10k 5 30 35 40 45 20 10 15 1m 10m code = 200 h 100 h 80 h 40 h 20 h 10 h 01 h 02 h 04 h 08 h tpc 12. gain vs. frequency vs. code, r ab = 10 k ? . test circuit in figure 18
rev. 0 ad5231 C9C frequency ?hz 0 ?0 1k gain ?db 100k 10k ?0 ?0 ?0 ?0 1m code = 200 h 10 h 04 h 08 h 100 h 80 h 40 h 20 h 01 h ?0 02 h tpc 13. gain vs. frequency vs. code, r ab = 50 k ? . test circuit in figure 18 frequency hz 0 50 1k gain db 100k 10k 30 40 20 10 1m code = 200 h 10 h 04 h 08 h 100 h 80 h 40 h 20 h 01 h 60 02 h tpc 14. gain vs. frequency vs. code, r ab = 100 k ? . test circuit in figure 18 r ab = 10k r ab = 50k r ab = 100k frequency hz psrr db 80 100 10k 1m 1k 100k 10m 70 50 30 20 0 60 40 10 v dd = +5.0v 100mv ac v ss = 0v, v a = 5v, v b = 0v measured at v w with code = 200 h tpc 15. psrr vs. frequency v dd v w 0.5v/div midscale 100 s/div 100 90 expected va l u e 10 0% tpc 16. power-on reset, v dd = 2.25 v, code = 1010101010 b time s v out v 2.55 01020 51525 2.53 2.51 2.49 2.47 2.45 v dd /v ss = 5v/0v code = 200 h to 1ff h r ab = 10k r ab = 50k r ab = 100k cs clk sdi idd 20ma/div 5v/div 5v/div 5v/div 4ms/div
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rev. 0 ad5231 C10C operational overview the ad5231 digital potentiometer is designed to operate as a true variable resistor replacement device for analog signals that remain within the terminal voltage range of v ss < v term < v dd . the basic voltage range is limited to a |v dd ?v ss | < 5.5 v. the digital potentiometer wiper position is determined by the rdac register contents. the rdac register acts as a scratch pad regis- ter allowing as many value changes as necessary to place the potentiometer wiper in the correct position. the scratch pad register can be programmed with any position value using the standard spi serial interface mode by loading the complete repre- sentative data word. once a desirable position is found this value can be saved into an eemem register. thereafter the wiper position will always be set at that position for any future on- off-on power supply sequence. the eemem save process takes approximately 25 ms, during this time the shift register is locked preventing any changes from taking place. the rdy pin indicates the completion of this eemem save. there are 16 instructions that facilitate users?programming needs. refer to table iii. the instructions are: 1. do nothing 2. restore eemem setting to rdac 3. save rdac setting to eemem 4. save rdac setting or user data to eemem 5. decrement 6 db 6. decrement 6 db 7. decrement one step 8. decrement one step 9. reset eemem setting to rdac 10. read eemem to sdo 11. read wiper setting to sdo 12. write data to rdac 13. increment 6 db 14. increment 6 db 15. increment one step 16. increment one step scratch pad and eemem programming the scratch pad register (rdac register) directly controls the position of the digital potentiometer wiper. when the scratch pad register is loaded with all zeros, the wiper will be connected to the b-terminal of the variable resistor. when the scratch pad register is loaded with midscale code (1/2 of full-scale position), the wiper will be connected to the middle of the variable resistor. and when the scratch pad is loaded with full-scale code, all ones, the wiper will connect to the a-terminal. since the scratch pad register is a standard logic register, there is no restriction on the number of changes allowed. the eemem registers have a program erase/write cycle limitation described in the flash/eemem reliability section. basic operation the basic mode of setting the variable resistor wiper position (programming the scratch pad register) is accomplished by loading the serial data input register with the command instruc- tion #11, which includes the desired wiper position data. when the desired wiper position is found, the user would load the serial data input register with the command instruction #2, which makes a copy of the desired wiper position data into the nonvolatile eemem register. after 25 ms the wiper position will be permanently stored in the nonvolatile eemem location. table i provides an application-programming example listing the sequence of serial data input (sdi) words and the serial data output appearing at the sdo pin in hexadecimal format. table i. set and save rdac data to eemem register sdi sdo action b00100 h xxxxxx h loads data 100 h into rdac register, wiper w moves to 1/4 full-scale position. 20xxxx h b00100 h saves copy of rdac register contents into eemem register. at system power on, the scratch pad register is automatically refreshed with the value last saved in the eemem register. the factory preset eemem value is midscale but thereafter, the eemem value can be changed by user. cs clk sdi i dd * 2ma/div 5v/div 5v/div 5v/div * supp ly current returns to minimum power consumption if instruction #0 (nop) is executed immediately after instruction #1 (read eemem) 4ms/div tpc 19. i dd vs. time (read) program mode code decimal 100 1 0.01 1024 theoretical i wb_max ma 0.1 10 r ab = 10k r ab = 50k r ab = 100k 896 768 640 512 384 128 256 0 v a = v b = open t a = 25 c tpc 20. i wb_max vs. code
rev. 0 ad5231 C11C during operation, the scratch pad (wiper) register can also be refreshed with the current content of the nonvolatile eemem register under hardware control by pulsing the pr pin without activating instruction 1 or 8. beware that the pr pulse first sets the wiper at midscale when brought to logic zero, and then on the positive transition to logic high, it reloads the rdac wiper register with the contents of eemem. many additional advanced programming commands are available to simplify the variable resistor adjustment process, see table iii. for example, the wiper position can be changed one step at a time by using the increment/decrement instruction or by 6 db at a time with the shift left/right instruc tion command. once an increment, decre- ment, or shift command has been loaded into the sh ift register, subsequent cs strobes will repeat this command. this is useful for push button control applications. see the advanced control modes section following the instruction operation truth table. a serial data output sdo pin is available for daisy-chaining and for readout of the internal register contents. the serial input data register uses a 24-bit [instruction/address/data] word format. eemem protection write protect ( wp ) disables any changes of the scratch pad register contents regardless of the software commands, except that the eemem setting can be refreshed and overwritten wp by using commands 1, 8, and pr pulse. therefore, the write- protect ( wp ) pin provides a hardware eemem protection feature. to disable wp , it is recommended to execute a nop command before returning wp to logic high. digital input/output configuration all digital inputs are esd-protected high-input impedance that can be driven directly from most digital sources. active at logic low, pr and wp must be biased to v dd if they are not used. no internal pull-up resistors are present on any digital input pins. the sdo and rdy pins are open-drain digital outputs where pull-up resistors are needed only if using these functions. a resistor value in the range of 1 k ? to 10 k ? is a proper choice which balances the power and switching speed trade off. the equivalent serial data input and output logic is shown in figure 3. the open drain output sdo is disabled whenever chip select cs is logic high. esd protection of the digital inputs is shown in figures 4a and 4b. va l i d command counter command processor and address decode serial register clk sdi 5v r pullup sdo gnd pr wp cs ad5231 figure 3. equivalent digital input-output logic logic pins v dd gnd input 300 figure 4a. equivalent esd digital input protection v dd gnd input 300 wp figure 4b. equivalent wp input protection serial data interface the ad5231 contains a four-wire spi compatible digital inter- face (sdi, sdo, cs , and clk). the ad5231 uses a 24-bit serial data word loaded msb first. the format of the spi com- patible word is shown in table ii. the chip select cs pin needs to be held low until the complete data word is loaded into the sdi pin. when cs returns high the serial data word is decoded according to the instructions in table iii. the command bits (cx) control the operation of the digital potentiometer. the address bits (ax) determine which register is activated. the data bits (dx) are the values that are loaded into the decoded register. table v provides an address map of the eemem locations. the last instruction executed prior to a period of no programming activity should be the no operation (nop) instruc- tion. this will place the internal logic circuitry in a minimum power dissipation state. the spi interface can be used in two slave modes cpha = 1, cpol = 1 and cpha = 0, cpol = 0. cpha and cpol refer to the control bits, that dictate spi timing in these microconverters and microprocessors: aduc812/aduc824, m68hc11, and mc68hc16r1/916r1. daisy-chain operation the serial data output pin (sdo) serves two purposes. it can be used to readout the contents of the wiper setting and eemem values using instructions 10 and 9, respectively. the remaining instructions (#0?8, #11?15) are valid for daisy-chaining multiple devices in simultaneous operations. daisy-chaining minimizes the number of port pins required from the controlling ic (see figure 5). the sdo pin contains an open drain n-ch fet that requires a pull-up resistor, if this function is used. as shown in figure 5, users need to tie the sdo pin of one package to the microconverter is a registered trademark of analog devices inc.
rev. 0 ad5231 C12C sdi pin of the next package. users may need to increase the clock period because the pull-up resistor and the capacitive loading at the sdo-sdi interface may require additional time delay between subsequent packages. when two ad5231s are daisy-chained, 48 bits of data are required. the first 24 bits go to u2 and the second 24 bits go to u1. the 24 bits are formatted to contain the 4-bit instruction, followed by the 4-bit address, 6-bit don? care, then the 10 bits of data. (the don? care can be used to store user information. see section using additional internal nonvolatile eemem). the cs should be kept low until all 48 bits are clocked into their respective serial registers. the cs is then pulled high to complete the operation. sdi sdo clk +v r p 2k c sdi sdo clk cs cs u1 u2 ad5231 ad5231 figure 5. daisy chain configuration using sdo terminal voltage operation range the ad5231 positive v dd and negative v ss power supply defines the boundary conditions for proper 3 terminal digital potentiometer operation. supply signals present on terminals a, b, a nd w that exceed v dd or v ss will be clamped by the internal for ward biased diodes (see figure 6). the ground pin of the ad5231 device is primarily used as a digital ground reference, which needs to be tied to the pcb? common ground. the digital input control signals to the ad5231 must be referenced to the device ground pin (gnd), and satisfy the logic level defined in the specification table of this data sheet. an internal level-shift circuit ensures that the common- mode voltage range of the three terminals extends from v ss to v dd , regardless of the digital input level. v ss v dd a w b figure 6. maximum terminal voltages set by v dd and v ss power-up sequence sinc e there are diodes to limit the voltage compliance at terminals a, b, and w (see figure 6), it is important to power v dd /v ss first before applying any voltage to terminals a, b, and w. otherwise, the diode will be forward-biased such that v dd / v ss will be powered uni ntentionally and may affect the rest of the user? circuit. the ideal power-up sequence is in the following order: gnd, v dd , v ss , digital inputs, and v a/b/w. the order of powering v a , v b , v w , and digital inputs are not important as long as they are powered after v dd /v ss . regardless of the power-up sequence and the ramp rates of the power supplies, once v dd /v ss are powered, the power-on reset remains effective, which retrieves eemem saved value to rdac register. latched digital outputs a pair of digital outputs, o1 and o2, is available on the ad5231 that provide a nonvolatile logic 0 or logic 1 setting. o1 and o2 are standard cmos logic outputs (shown in figure 7). these outputs are ideal to replace functions often provided by dip switches. in addition, they can be used to drive other standard cmos logic controlled parts that need an occasional setting change. v dd gnd outputs o1 and o2 pins figure 7. logic outputs o1 and o2
rev. 0 ad5231 C13C table iii. instruction/operation truth table 1, 2, 3 instruction byte 0 data byte 1 data byte 0 instruction b23 ?b16 b15 ?b8 b7 ?b0 number c3 c2 c1 c0 a3 a2 a1 a0 x ?d9 d8 d7 ?d0 operation 0 0 0 0 0 x x x x x ?x x x x nop: do nothing. see table xi 1 0 0 0 1 0 0 0 a0 x ?x x x x write content of eemem to rdac register. this command leaves device in the read pro- gram power state. to return part to the idle state, perform nop instruction #0. see table xi 2 0 0 1 0 0 0 0 a0 x ?x x x ?x save wiper setting: write contents of rdac to eemem. see table x 3 4 0 0 1 1 a3 a2 a1 a0 d15 ?d8 d7 ?d0 write contents of serial register data bytes 0 and 1 (total 16-bit) to eemem(addr). see table xiii 4 5 0 1 0 0 0 0 0 a0 x ?x x x ?x decrement 6 db: right shift contents of rdac, stops at all ?eros. 5 5 0 1 0 1 x x x x x ?x x x ?x same as instruction 4 6 5 0 1 1 0 0 0 0 a0 x ?x x x ?x decrement content of rdac register by ?ne, stops at all ?eros. 7 5 0 1 1 1 x x x x x ?x x x ?x same as instruction 6 8 1 0 0 0 x x x x x ?x x x ?x reset: load rdac with its corresponding eemem previously saved value. 9 1 0 0 1 a3 a2 a1 a0 x ?x x x ?x write content of eemem(addr) to serial register data bytes 0 and 1. sdo activated. see table xiv 10 1 0 1 0 0 0 0 a0 x ?x x x ?x write content of rdac to serial register data bytes 0 and 1. sdo activated. see table xv 11 1 0 1 1 0 0 0 a0 x ?d9, d8 d7 ?d0 write content of serial register data bytes 0 and 1 (total 10-bit) to rdac register. see table ix 12 5 1 1 0 0 0 0 0 a0 x ?x x x ?x increment 6 db: left shift content of rdac, stops at all ?nes.?see table xii 13 5 1 1 0 1 x x x x x ?x x x ?x same as instruction 12 14 5 1 1 1 0 0 0 0 a0 x ?x x x ?x increment content of rdac register by ?ne, stops at all ?nes.?see table x. 15 5 1 1 1 1 x x x x x ?x x x ?x same as instruction 14 notes 1 the sdo output shifts out the last 24 bits of data clocked into the serial register for daisy-chain operation. exception, any i nstruction following instruction #9 or #10, the selected internal register data will be present in data bytes 0 and 1. the instruction following #9 and #10 must also be a full 24-bit data word to completely clock out the contents of the serial register. 2 the rdac register is a volatile scratch pad register that is refreshed at power on from the corresponding nonvolatile eemem reg ister. 3 execution of the above operations takes place when the cs strobe returns to logic high. 4 instruction #3 write two data bytes (16-bit data) to eemem. in the case of 0 addresses, only the last 10 bits are valid for wip er position setting. 5 the increment, decrement, and shift commands ignore the contents of the shift register data bytes 0 and 1. table ii. ad5231 24-bit serial data word msb instruction byte 0 data byte 1 data byte 0 lsb rdac c3 c2 c1 c0 000a0 xxxxxxd9d8d7d6d5d4d3d2d1d0 eemem c3 c2 c1 c0 a3 a2 a1 a0 ddddddd9d8d7d6d5d4d3d2d1d0 15 14 13 12 11 10 command bits are c0 to c3. address bits are a3 to a0. data bits d0 to d9 are applicable to rdac; d0 to d15 are applicable to ee mem. command instruction codes are defined in table iii.
rev. 0 ad5231 C14C advanced control modes the ad5231 digital potentiometer contains a set of user pro- gramming features to address the wide applications available to these universal adjustment devices. key programming features include: ? scratch pad programming to any desirable values ? nonvolatile memory storage of the present scratch pad rdac register value into the eemem register ? increment and decrement instructions for rdac wiper register ? left and right bit shift of rdac wiper register to achieve 6 db level changes ? 28 extra bytes of user-addressable nonvolatile memory linear increment and decrement commands the increment and decrement commands (#14, #15, #6, #7) are useful for linear step adjustment applications. these commands simplify microcontroller software coding by allowing the controller to just send an increment or decrement command to the device. for increment command, executing instruction #14 with proper address will automatically move the wiper to the next resistance segment position. instruction #15 performs the same function except address does not need to be specified. logarithmic taper mode adjustment ( 6 db/step) four programming instructions produce logarithmic taper increment and decrement wiper. these settings are activated by the 6 db increment and 6 db decrement instructions #12, #13, #4, and #5, respectively. for example, starting at zero scale, executing 11 times the increment instruction #12 will move the wiper in +6 db per step from the 0% to full scale r ab . the +6 db increment instruction doubles the value of the rdac register content each time the command is executed. when the wiper position is near the maximum setting, the last +6 db increment instruction will cause the wiper to go to the full-scale 1023 code position. further +6 db per increment instruction will no longer change the wiper position beyond its full scale. 6 db step increment and decrement are achieved by shifting the bit internally to the left and right, respectively. the following infor- mation explains the nonideal 6 db step adjustment at certain conditions. table iv illustrates the operation of the shifting function on the rdac register data bits. each line going down the table represents a successive shift operation. note that the left shift #12 and #13 commands were modified such that if the data in the rdac register is equal to zero, and the data is left shifted, the rdac register is then set to code 1. similarly, if the data in the rdac register is greater than or equal to midscale, and the data is left shifted, then the data in the rdac register is automati- cally set to full-scale. this makes the left shift function as ideal a logarithmic adjustment as possible. the right shift #4 and #5 commands will be ideal only if the lsb is zero (i.e., ideal logarithmic?o error). if the lsb is a 1, the right shift function generates a linear half lsb error, which translates to a numbers of bits dependent logarithmic error as shown in figure 8. the plot shows the error of the odd numbers of bits for ad5231. table iv. detail left and right shift functions for 6 db step increment and decrement left shift right shift 00 0000 0000 11 1111 1111 00 0000 0001 01 1111 1111 00 0000 0010 00 1111 1111 00 0000 0100 00 0111 1111 00 0000 1000 00 0011 1111 00 0001 0000 00 0001 1111 00 0010 0000 00 0000 1111 00 0100 0000 00 0000 0111 00 1000 0000 00 0000 0011 01 0000 0000 00 0000 0001 10 0000 0000 00 0000 0000 11 1111 1111 00 0000 0000 11 1111 1111 00 0000 0000 actual conformance to a logarithmic curve between the data contents in the rdac register and the wiper position for each right shift #4 and #5 command execution contains an error only for odd numbers of bits. even numbers of bits are ideal. the graph in figure 8 shows plots of log_error [i.e., 20 log 10 (error/code)] ad5231. for example, code 3 log_error = 20 log 10 (0.5/3) = ?5.56 db, which is the worst case. the plot of log_error is more significant at the lower codes. code from 1 to 1023 by 2.0 10 3 0 0 db 40 60 80 20 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 figure 8. plot of log_error conformance for odd numbers of bits only (even numbers of bits are ideal) using additional internal nonvolatile eemem the ad5231 contains additional internal user storage registers (eemem) for saving constants and other 16-bit data. table v provides an address map of the internal storage registers shown in the functional block diagram as eemem1, eemem2, and 28 bytes (14 addresses 2 bytes each) of user eemem. table v. eemem address map address eemem for 0000 rdac 1, 2 0001 o1 and o2 3 0010 user1 4 0011 user2 :: 1110 user13 1111 user14 right shift (? db/step) left shift (+6 db/step)
rev. 0 ad5231 C15C part. for v dd = 5 v, the wiper first connection starts at the b terminal for data 000 h . r wb (0) is 15 ? because of the wiper resistance and it is independent of the nominal resistance. the second connection is the first tap point where r wb (1) becomes 9.7 ? + 15 ? = 27.4 ? for data 001 h . the third connection is the next tap point representing r wb (2) = 19.4 + 15 = 34.4 ? for data 002 h and so on. each lsb data value increase moves the wiper up the resistor ladder until the last tap point is reached at r wb (1023) = 10005 ? . see figure 9 for a simplified diagram of the equivalent rdac circuit. when r wb is used, the aCterminal can be left floating or tied to the wiper. code decimal 100 75 0 0 1023 256 r wa (d), r wb (d) % of nominal r ab 512 768 50 25 r wb r wa figure 10. r wa (d) and r wb (d) vs. decimal code the general equation, which determines the programmed output resistance between w and b, is: rd d rr wb ab w () =+ 1024 (1) where d is the decimal equivalent of the data contained in the rdac register, r ab is the nominal resistance between terminals a-and-b, and r w is the wiper resistance. for example, the following output resistance values will be set for the following rdac latch codes with v dd = 5 v (applies to r ab = 10 k ? digital potentiometers): table vii. r wb at selected codes for r ab = 10 k ? d(dec) r wb (d) ( ? ) output state 1023 10,005 full-scale 512 50015 midscale 1 24.7 1 lsb 0 15 zero-scale (wiper contact resistor) note that in the zero-scale condition a finite wiper resistance of 15 ? is present. care should be taken to limit the current flow between w and b in this state to no more than 20 ma to avoid degradation or possible destruction of the internal switches. like the mechanical potentiometer the rdac replaces, the ad5231 parts are totally symmetrical. the resistance between the wiper w and terminal a also produces a digitally controlled complementary resistance r wa . figure 10 shows the symmetrical programmability of the various terminal connections. when r wa is used, the b-terminal can be let floating or tied to the wiper. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded in the latch is in creased in value. the general transfer equation for this operation is: notes 1 rdac data stored in eemem location is transferred to the rdac register at power on, or when instructions #1, #8, and pr are executed. 2 execution of instruction #1 leaves the device in the read mode power con- sumption state. after the last instruction #1 is executed, the user should perform a nop, instruction #0 to return the device to the low power idling state. 3 o1 and o2 data stored in eemem locations are transferred to their corresponding digital register at power on, or when instructions #1 and #8 are executed. 4 user are internal nonvolatile eemem registers available to store and retrieve constants and other 16-bit information using #3 and #9, respectively. rdac structure the patent pending rdac contains multiple strings of equal resistor segments, with an array of analog switches, that act as the wiper connection. the number of positions is the resolution of the device. the ad5231 has 1024 connection points allowing it to provide better than 0.1% set-ability resolution. figure 9 shows an equivalent structure of the connections between the three terminals of the rdac. the sw a and sw b will always be on, while one of the switches sw(0) to sw(2 n C1) will be on one at a time depending on the resistance position decoded from the data bits. since the switch is not ideal, there is a 15 ? wiper resistance, r w . wiper resistance is a function of supply voltage and temperature. the lower the supply voltage, or the higher the temperature, the higher the resulting wiper resistance. users should be aware of the wiper resistance dynamics if accu- rate prediction of the output resistance is needed. sw (1) sw (0) sw b b r s r s sw a sw(2 n 1) a w sw(2 n 2) rdac wiper register and decoder r s = r ab /2 n r s digital circuitry omitted for clarity figure 9. equivalent rdac structure (patent pending) table vi. nominal individual segment resistor (r s ) device 10 k 50 k 100 k resolution version version version 10-bit 9.8 ? 48.8 ? 97.6 ? programming the variable resistor rheostat operation the nominal resistance of the rdac between terminals a-and- b, r ab is available with 10 k ? , 50 k ? , and 100 k ? with 1024 positions (10-bit resolution). the final digit(s) of the part number determine the nominal resistance value, e.g., 10 k ? = 10; 50 k ? = 50; 100 k ? = c. the 10-bit data word in the rdac latch is decoded to select one of the 1024 possible settings. the following discussion describes the calculation of resistance r wb at different codes of a 10 k ?
rev. 0 ad5231 C16C rd d rr wa ab w () ? =+ 1024 1024 (2) for example, the following output resistance values will be set for the following rdac latch codes with v dd = 5 v (applies to r ab = 10 k ? digital potentiometers): table viii. r wa (d) at selected codes for r ab = 10 k ? d(dec) r wa (d) ( ? ) output state 1023 24.7 full-scale 512 5015 midscale 1 10005 1 lsb 0 10015 zero-scale the typical distribution of r ab from device-to device matches tightly when they are processed at the same batch. when devices are pro- cessed at different time, device-to device matching becomes process lot dependent and exhibits a C40% to +20% variation. the change in r ab with temperature has a 600 ppm/ c temperature coefficient. programming the potentiometer divider voltage output operation the digital potentiometer can be configured to generate an output voltage at the wiper terminal which is proportional to the input voltages applied to terminals a and b. for example con- necting a-terminal to 5 v and b-terminal to ground produces an output voltage at the wiper which can be any value starting at 0 v up to 5 v. each lsb of voltage is equal to the voltage applied across terminal ab divided by the 2 n position resolution of the potentiometer divider. since ad5231 can also be supplied by dual supplies, the general equation defining the output voltage at v w with respect to ground for any given input voltages applied to terminals a and b is: vd d vv wabb () =+ 1024 (3) equation 3 assumes v w is buffered so that the effect of wiper resistance is nulled. operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. here the output voltage is dependent on the ratio of the internal resistors and not the absolute value, therefore, the drift improves to 15 ppm/ c. there is no voltage polarity restriction between terminals a, b, and w as long as the terminal voltage (v term ) stays within v ss < v term < v dd . programming examples the following programming examples illustrate typical sequence of events for various features of the ad5231. users should refer to table iii for the instructions and data word format. the instruction numbers, addresses, and data appearing at sdi and sdo pins are based in hexadecimal in the following examples. table ix. scratch pad programming sdi sdo action b00100 h xxxxxx h loads data 100 h into rdac register, wiper w moves to 1/4 full-scale position. table x. incrementing rdac followed by storing the wiper setting to eemem sdi sdo action b00100 h xxxxxx h loads data 100 h into rdac register, wiper w moves to 1/4 full-scale position. e0xxxx h b00100 h increments rdac register by one to 101 h . e0xxxx h e0xxxx h increments rdac register by one to 102 h . continue until desired wiper position is reached. 20xxxx h xxxxxx h saves rdac register data into eemem. optionally tie wp to gnd to protect eemem values. table xi. restoring eemem value to rdac register eemem value for rdac can be restored by power on, or strobing pr pin, or programming shown below. sdi sdo action 10xxxx h xxxxxx h restores eemem value to rdac register. 00xxxx h 10xxxx h nop. recommended step to minimize power consumption. 8xxxxx h 00xxxx h reset eemem value to rdac register. table xii. using left shift by one to increment +6 db step sdi sdo action c0xxxx h xxxxxx h moves wiper to double the present data contained in rdac register. table xiii. storing additional user data in eemem sdi sdo action 32aaaa h xxxxxx h stores data aaaa h into spare eemem location user1. (allowable to address in 14 locations with maximum 16 bits of data.) 335555 h 32aaaa h stores data 5555 h into spare eemem location user2. (allowable to address in 14 locations with maximum 16 bits of data.) table xiv. reading back data from various memory locations sdi sdo action 92xxxx h xxxxxx h prepares data read from user1 location. 00xxxx h 92aaaa h nop instruction #0 sends 24-bit word out of sdo where the last 16 bits contain the contents of user1 location. nop command ensures device returns to idle power dissi- pation state.
rev. 0 ad5231 C17C table xv. reading back wiper settings sdi sdo action b00200 h xxxxxx h sets rdac to midscale. c0xxxx h b00200 h doubles rdac from midscale to full-scale. (left shift instructions) a0xxxx h c0xxxx h prepares reading wiper setting from rdac register. xxxxxx h a003ff h readback full-scale value from rdac register. test circuits figures 11 to 19 define the test conditions used in the product specifications table. a w b nc i w dut v ms nc = no connect figure 11. resistor position nonlinearity error (rheostat operation; r-inl, r-dnl) a w b dut v ms v+ v+ = v dd 1lsb = v+/2 n figure 12. potentiometer divider nonlinearity error test circuit (inl, dnl) a w b dut i w v ms1 v ms2 v w r w = [ v ms1 v ms2 ] /i w figure 13. wiper resistance test circuit a w b v ms v+ = v dd 10% psrr (db) = 20 log v ms v dd ( ) ~ v a v dd v ms % v dd % pss (%/%) = v+ figure 14. power supply sensitivity test circuit (pss, psrr) offset bias offset gnd ab dut w 5v v in v out op279 figure 15. inverting gain test circuit offset bias offset gnd ab dut w 5v v in v out op279 figure 16. noninverting gain test circuit offset gnd a b dut w +15v v in v out op42 15v 2.5v figure 17. gain vs. frequency test circuit + _ dut code = h 0.1v v bias r sw = 0.1v i sw i sw w b a = nc "
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rev. 0 ad5231 C18C flash/eemem reliability the flash/ee memory array on the ad5231 is fully qualified for two key flash/ee memory characteristics, namely flash/ee memory cycling endurance and flash/ee memory data retention. endurance quantifies the ability of the flash/ee memory to be cycled through many program, read, and erase cycles. in real terms, a single endurance cycle is composed of four independent, sequential events. these events are defined as: ? initial page erase sequence ? read/verify sequence ? byte program sequence ? second read/verify sequence during reliability qualification flash/ee memory is cycled from 000 h to 3ff h until a first fail is recorded signifying the endurance limit of the on-chip flash/ee memory. as indicated in the specification pages of this data sheet, the ad 5231 flash/ee memory endurance qualification has been carried out in accordance with jedec specification a117 over the industrial temperature range of C40 c to +85 c. the results allow the specification of a minimum endurance figure over supply and temperature of 100,000 cycles, with an endurance figure of 700,000 cycles being typical of operation at 25 c. retention quantifies the ability of the flash/ee memory to retain its programmed data over time. again, the ad5231 has been qualified in accordance with the formal jedec retention lifetime specification (a117) at a specific junction temperature (t j = 55 c). as part of this qualification procedure, the flash/ee memory is cycled to its specified endurance limit described above, before data retention is characterized. this means that the flash/ee memory is guaranteed to retain its data for its full specified retention lifetime every time the flash/ee memory is reprogrammed. it should also be noted that retention lifetime, based on an activation energy of 0.6 ev, will derate with t j as shown in figure 20. for example, the data is retained for 100 years at 55 c operation, but reduces to 15 years at 85 c operation. beyond such limit, the part must be reprogrammed so that the data can be restored. t j junction temperature c 300 250 0 40 retention years 200 150 100 50 50 60 70 80 90 100 110 adi typical performance at t j = 55 c figure 20. flash/ee memory data retention applications bipolar operation from dual supplies the ad5231 can be operated from dual supplies 2.5 v, which enables control of ground referenced ac signals or bipolar opera tion. ac signal, as high as v dd /v ss , can be applied directly across terminals a-b with output taking from terminal w. (see figure 21 for a typical circuit connection.) 2.5v p-p ad5231 v ss gnd sdi clk ss sclk mosi gnd v dd c 1.25v p-p v dd +2.5v 2.5v cs d = midscale a w b figure 21. bipolar operation from dual supplies high voltage operation the digital potentiometer can be placed directly in the feedback or input path of an op amp for gain control, provided that the voltage across terminals a-b, w-a, or w-b does not exceed |5 v|. when high voltage gain is needed, users should set a fixed gain in an op amp operated at +15 v, and let the digital potentiometer control the adjustable input. figure 22 shows a simple implementation. r2r 5v ad5231 a w b 15v v+ v v o 0 to 15v a1 + figure 22. 15 v voltage span control bipolar programmable gain amplifier there are several ways to achieve bipolar gain. figure 23 shows one versatile implementation. digital potentiometer u1 sets the adjustment range, the wiper voltage v w2 can therefore be programmed between v i and Ckv i at a given u2 setting. for linear adjustment, configure a2 as a noninverting amplifier and the trans- fer function becomes: v v r r d kk o i =+ ? ? ? ? + () ? ? ? ? ? ? 1 2 1 1024 1 2 ? (4) where: k is the ratio of r wb /r wa which is set by u1. d = decimal equivalent of the input code
rev. 0 ad5231 C19C v+ v op2177 ad5231 v o v+ v op2177 ad5231 vi a w b kvi a b w v dd v ss r1 r2 v dd v ss a u2 a2 u1 figure 23. bipolar programmable gain amplifier in the simpler (and much more usual) case where k = 1, a pair of matched resistors can replace u1. equation 4 simplifies to: v v r r d o i =+ ? ? ? ? ? ? ? ? 1 2 1 2 1024 1 2 ? (5) table xvi shows the result of adjusting d with a2 configured as a unity gain, a gain of 2, and a gain of 10. the result is a bipolar amplifier with linearly programmable gain and 1024-step resolution. table xvi. result of bipolar gain amplifier d r1 = , r2 = 0 r1 = r2 r2 = 9 r1 0 C1 C2 C10 256 C0.5 C1 C5 512 0 0 0 768 0.5 1 5 1023 0.992 1.984 9.92 10-bit bipolar dac if the circuit is changed in figure 23 with the input taking from a voltage reference and configure a2 as a buffer, a 10-bit bipolar dac can be realized. compared to the conventional dac, this circuit offers comparable resolution but not the precision because of the wiper resistance effects. degradation of the nonlinearity and temperature coefficient are prominent near both ends of the adjustment range. on the other hand, this circuit offers a unique nonvolatile memory feature which in some cases outweigh the shortfall of nonprecision. the output of this circuit is: v d v o ref = ? ? ? ? ? ? 2 1024 1 2 C (6) v+ v ad8552 ad5231 v o v+ v ad8552 2.5vref b a w a1 u1 +2.5vref v in v out trim gnd adr421 +5v 5v 5v +5v rr a2 +5v figure 24. 10-bit bipolar dac programmable voltage reference for programmable voltage divider mode operation (figure 25) it is common to buffer the output of the digital potentiometer unless the load is much larger than the source resistance r wb . in addition, the current handling of the digital potentiometer is limited by its maximum operating voltage, power dissipation, and the maximum current handling of the internal switches at a given resistance (see tpc 20). as a result, the added buffer can be used to deliver the current needed to the load as long as it is within its current handling capability. ad5231 v+ v ad8601 w a1 v in v out gnd ad1582 5v 5v u1 3 a b v o 1 2 figure 25. programmable voltage reference programmable voltage source with boosted output for applications such as laser diode driver or turnable laser, requiring high current adjustment a boosted voltage source can be considered (see figure 26). ad5231 v+ v w a1 v bias 5v a b v s n1 p1 r bias signal c c ld i bias r1 10k a1 = ad8601, ad8605, ad8541 p1 = fdp360p, nds9430 n1 = fdv301n, 2n7002 figure 26. boosted voltage source in this circuit, the inverting input of the op amp forces the v bias to be equal to the wiper voltage set by the digital potenti- ometer. the load current is then delivered by the supply via the p-ch fet p1. the n-ch fet n1 simplifies the op amp driving requirement. resistor r1 is needed to prevent p1 for not turning off once it is on. the choice of r1 is a balance between the power loss of this resistor and the output turn off time. n1 can be any general purpose signal fet; on the other hand, p1 is driven in the saturation state and therefore its power handling must be adequate to dissipate (v s C v bias ) i bias power. this circuit can source maximum of 100 ma at 5 v supply. higher current can be achieved with p1 in larger package. note a single n-ch fet can replace p1, n1, and r1 altogether. however, the output swing will be limited unless separate power supplies are used. for precision application, a voltage reference such as adr423, adr292, and ad1584, can be applied at the input of the digital potentiometer.
rev. 0 ad5231 C20C programmable 4 ma to 20 ma current source a programmable 4 ma to 20 ma current source can be imple- mented with the circuit shown in figure 27. v+ v op1177 u2 vin sleep ref191 gnd vout 3 2 4 6 u1 c1 1 f ad5231 w a b r s 102 r l 100 v l i l +5v 2.048v to v l 5v 0 to (2.048 + v l ) +5v + figure 27. programmable 4 ma to 20 ma current source ref191 is a unique low supply headroom precision reference that can deliver the 20 ma needed at 2.048 v. the load current is simply the voltage across terminals b-to-w of the digital potentiometer divided by r s : i vd r l ref s = ? ? ? ? ? ? (7) the circuit is simple, but be aw are that there are two issues. first, dual supply op amps are ideal because the ground potential of ref191 can swing from C2.048 v at zero scale to v l at full scale of the potentiometer setting. although the circuit works under single supply, the programmable resolution of the system will be reduced. second, the voltage compliance at v l is limited to 2.5 v or equivalently a 125 ? load. should higher voltage compliance be needed, users may consider digital potentiometers ad5260, ad5280, and ad7376. figure 28 below shows an alternate circuit for high voltage compliance. programmable bidirectional current source for applications that require bidirectional current control or higher voltage compliance, a howland current pump can be a solution. if the resistors are matched, the load current is: i ra rb r rb v lw = + () 22 1 2 (8) 15v op2177 v+ v +15v + c1 10pf r2 15k r1 150k r2b 50 r l 500 v l r2a 14.95k r1 150k c2 10pf i l op2177 v+ v +15v + 15v a1 ad5231 a b w +2.5v 2.5v a2 figure 28. programmable bidirectional current source r2b in theory can be made as small as needed to achieve the current needed within a2 output current driving capability. in this circuit op2177 delivers 5 ma in both directions and the voltage compliance approaches 15 v. it can be shown that the output impedance is: z r rr rr o = ? ? ? ? ? ? 1 12 12 1 ' ' ? (9) z o can be infinite if resistors r 1 and r 2 match precisely with r 1 and r 2a + r 2b respectively. on the other hand, z o can be nega- tive if the resistors are not matched. as a result, c1 and c2, in the range of 1 pf to 10 pf, are needed to prevent the oscillation. resistance scaling ad5231 offers 10 k ? , 50 k ? , and 100 k ? nominal resistance. for users who need lower resistance but want to maintain the numbers of step adjustment, they can parallel multiple devices. for example, figure 29 shows a simple scheme of paralleling two ad5231. in order to adjust half of the resistance linearly per step, users need to program both devices coherently with the same settings and tie the terminals as shown. a1 b1 w1 w2 a2 b2 ld figure 29. reduce resistance by half with linear adjustment characteristics in voltage divider mode, a much lower resistance can be achieved by paralleling a discrete resistor as shown in figure 30. the equiva- lent resistance become: r d rr r wb eq w = () + 1024 12 // (10) r d rr r wa eq w = ? ? ? ? () + 1 1024 12 ?// (11) r2 r1 b w r2 << r1 a figure 30. lowering the nominal resistance figures 29 and 30 show that the digital potentiometers change steps linearly. on the other hand, log taper adjustment is usually preferred in applications like audio control. figure 31 shows another way of resistance scaling. in this configuration, the smaller the r2 with respect to r1, the more the pseudo log taper characteristic behaves.
rev. 0 ad5231 C21C r1 r2 v o a b w figure 31. resistor scaling with pseudo log adjust- ment characteristics rdac circuit simulation model the internal parasitic capacitances and the external load dominates the ac characteristics of the rdacs. configured as a potentiom- eter divider the C3 db bandwidth of the ad5231bru10 (10 k ? resistor) measures 370 khz at half scale. tpc 10 provides the large signal bode plot characteristics. a parasitic simulation mode is shown in figure 32. listing i provides a macro model net list for the 10 k ? rdac: ab rdac 10k w c w 50pf c b 50pf c a 50pf figure 32. rdac circuit simulation model for rdac = 10 k ? listing i. macro model net list for rdac .param d = 1024, rdac = 10e3 * .subckt dpot (a, w, b) * ca a 0 50e-12 raw a w {(1-d/1024)*rdac+15} cw w 0 50e-12 rbw w b {d/1024*rdac+15} cb b 0 50e-12 * .ends dpot
rev. 0 ad5231 C22C digital potentiometer family selection guide resolution power number terminal interface nominal (number supply part of vrs per voltage data resistance of wiper current number package range (v) control (k ) positions) (i dd ) ( a) packages comments ad5201 1 3, +5.5 3-wire 10, 50 33 40 soic-10 full ac specs, dual supply, power-on reset, low cost ad5220 1 5.5 up/ 10, 50, 100 128 40 pdip, so-8, no rollover, down soic-8 power-on reset ad7376 1 15, +28 3-wire 10, 50, 100, 128 100 pdip-14, single 28 v 1000 sol-16, or dual 15 v tssop-14 supply operation ad5200 1 3, +5.5 3-wire 10, 50 256 40 soic-10 full ac specs, dual supply, power-on reset ad8400 1 5.5 3-wire 1, 10, 50, 100 256 5 so-8 full ac specs ad5260 1 5, +15 3-wire 20, 50, 200 256 60 tssop-14 5 v to 15 v or 5 v operation, tc < 50 ppm/ c ad5241 1 3, +5.5 2-wire 10, 100, 1000 256 50 so-14, i 2 c compatible, tssop-14 tc < 50 ppm/ c ad5231 1 2.75, +5.5 3-wire 10, 50, 100 1024 20 tssop-16 nonvolatile memory, direct program, i/d, 6 db settability ad5222 2 3, +5.5 up/ 10, 50, 100, 128 80 so-14, no rollover, stereo down 1000 tssop-14 power-on reset, tc < 50 ppm/ c ad8402 2 5.5 3-wire 1, 10, 50, 100 256 5 pdip, so-14, full ac specs, na tssop-14 shutdown current ad5207 2 3, +5.5 3-wire 10, 50, 100 256 40 tssop-14 full ac specs, dual supply, power-on reset, sdo ad5232 2 2.75, +5.5 3-wire 10, 50, 100 256 20 tssop-16 nonvolatile memory, direct program, i/d, 6 db settability ad5235 2 2.75, +5.5 3-wire 25, 250 1024 20 tssop-16 nonvolatile memory, direct program, tc < 50 ppm/ c ad5242 2 3, +5.5 2-wire 10, 100, 1000 256 50 so-16, i 2 c compatible, tssop-16 tc < 50 ppm/ c ad5262 2 5, +15 3-wire 20, 50, 200 256 60 tssop-16 5 v to 15 v or 5 v operation, tc < 50 ppm/ c ad5203 4 5.5 3-wire 10, 100 64 5 pdip, full ac specs, na sol-24, shutdown current tssop-24 ad5233 4 2.75, +5.5 3-wire 10, 50, 100 64 20 tssop-24 nonvolatile memory, direct program, i/d, 6 db settability ad5204 4 3, +5.5 3-wire 10, 50, 100 256 60 pdip, full ac specs, sol-24, dual supply, tssop-24 power-on reset ad8403 4 5.5 3-wire 1, 10, 50, 100 256 5 pdip, full ac specs, na sol-24, shutdown current tssop-24 ad5206 6 3, +5.5 3-wire 10, 50, 100 256 60 pdip, full ac specs, sol-24, dual supply, tssop-24 power-on reset
rev. 0 ad5231 C23C 16-lead tssop (ru-16) 16 9 8 1 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.201 (5.10) 0.193 (4.90) seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 outline dimensions dimensions shown in inches and (mm).
C24C c02739C.8C10/01(0) printed in u.s.a.

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